1. Field of the Invention
The field of the present invention pertains to circuitry to solve the problems caused by capacitive and inductive coupling in signals in an integrated circuit device. This particular issue of capacitive and inductive coupling in signals is becoming increasingly difficult as the industry advances and moves towards reduction in circuit device size (for example, from 0.25 uM technology to 0.18 uM, 0.15 uM, 0.13 uM and beyond).
2. Related Art
With their growth in commercial markets and consumer demands for smaller Integrated Circuits (ICsxe2x80x94which are used in numerous applications such as cellular phones, wristwatch cameras, and hand-held organizers just to name a few) increase, IC size requirement trends continue towards a small form factor and lowered power consumption. As these IC size requirements shrink, semiconductor manufacturers are forced to design circuits at a much smaller level than in the past. Previously, as the industry moved from Very Large Scale Integration (VLSI) to Ultra Large Scale Integration (ULSI), the relative capacitive and inductive coupling of the circuit itself was not realized to be as critical of an issue.
However, as the semiconductor industry designs and implements circuitry on sub-micron level technology (where spacing between circuitry lines is less than 10xe2x88x926 m) and beyond, the capacitive and inductive coupling of the signal lines within the circuitry itself is realized to be a critical problem for designers. As circuit size becomes smaller and the relative distances for signal lines becomes longer, the problem of coupling and or cross talk between signal lines and ground or power lines becomes more evident. Furthermore, as the signal line to ground coupling and/or other signal lines becomes stronger, the signal to noise ratio for given signals increases proportionally. This particular issue of capacitive and inductive coupling in signals is becoming increasingly difficult as the industry advances and moves towards reduction in circuit device size (for example, from 0.25 uM technology to 0.18 uM, 0.15 uM, 0.13 uM and beyond).
One prior art approach to minimize the signal to noise ratio (or capacitive and inductive coupling), is to strengthen the signal drive level. By increasing the signal strength, the total signal to noise ratio is reduced. Unfortunately, to increase the signal strength, the device must also be supplied higher power. This solution is inconsistent with the modern trend of reducing power consumption in ICs for heat issues, portability issues and environmental issues.
In addition to higher power requirement, this prior art approach does not eliminate the coupling issue.
Another prior art approach is to reduce the effective (R-L-C) impedance of the signal lines and thereby increasing the spacing between signal lines. In general, increasing the spacing between signal lines by three-fold, the coupling effect will only be reduced by fifty percent. This prior art approach is usually combined with the first prior art approach to minimize coupling and reduce signal to noise ratio. This approach is inconsistent with modern trends for circuit compactness.
Yet another prior art approach is to shield the signal lines by using either a supply voltage like VDD or ground. Utilizing this prior art approach, the shielding line (ground) would need to be wide enough (with low impedance) so that the shield itself will not begin to transfer the noise to other signal lines.
These prior art approaches that tend to compensate by increasing signal strength combined with the prior art approach of providing a shielding line adjacent to signal line are shown in FIG. 1. As shown in this depiction, 100, the signal line 110 is routed along with the shielding line 120, which is then utilized to shield the noise from a neighboring signal line. For sub-micron technologies, the lengths of these signal and shield lines can become relatively long with respect to line thickness and thus can lead to high signal to noise ratio or cross-talk within a said circuit on a given substrate.
Therefore, a need exists for reducing the capacitive and inductive signal coupling effects of routing resources of an IC device.
Accordingly, the present invention minimizes and reduces the signal coupling effects caused by capacitive and/or inductive signal coupling effects of routing in an integrated circuit device. These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.
The present invention discloses a circuit composed of a power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing an integrated circuit device. The shield mesh is included in addition to the power and ground grid typically provided in an IC. The units of the shield mesh are placed such that they surround routing resources of the integrated circuit. Specifically, one embodiment of the present invention describes a method of routing a shield mesh of both power and ground lines to remove noise created by capacitive and inductive coupling. Alternating mesh lines of VDD and VSS (or ground) are laid down and signal routing resources are placed in-between. The shield mesh can be single or multi-layered. The shield mesh is included in addition to a power grid and may be connected to the power grid.
As Very Deep Sub-Micron (VDSM) technologies continue to reduce in size (for example from 0.18 uM, 0.15 uM, 0.13 uM, 0.11 uM and beyond), the signal lines become even more susceptible to capacitive and inductive coupling and noise from other neighboring signal lines. Relatively long signal lines are routed in between fully connected power and ground shielding mesh which is typically generated by a router during the signal routing phase or during power mesh routing phase. In one embodiment, leaving only the odd tracks or the even tracks for signal routing, power mesh (VDD) and ground mesh (VSS) are routed and fully interconnected leaving shorter segments and thereby reducing the RC effect of the circuit device.
Another embodiment of the invention describes a technique where the signals are shielded using the power and ground mesh for a gridless routing. Another embodiment of the invention presents a multi-layer grid routing technique where signals are routed on an even grid and the power and ground lines are routed on an odd grid. A similar embodiment of the invention represents grid routing technique where the signals are routed between layers N and N+1. While another embodiment of the invention enables signals to be shielded by opposite power and ground grids on left, right, top and bottom. Additional embodiments of the invention also include utilization of similar mesh utilized in standard cell and/or in the gate array routing area or any other area where any other signal line is to be shielded, thereby reducing the effective resistive or RC component of the power or grounding lines.
More specifically, an embodiment of the present invention is drawn to an integrated circuit device comprising: a) a plurality of signal lines disposed within a substrate; b) a power grid disposed on the substrate and comprising: a plurality of power lines having a first thickness; and a plurality of ground lines having the first thickness, the power grid for supplying power and ground to circuitry of the substrate; and c) a shield mesh disposed on the substrate and comprising: a plurality of power lines having a second thickness; and a plurality of ground lines having the second thickness, wherein respective signal lines of the plurality of signal lines are disposed between a respective power line of the shield mesh and a respective ground line of the shield mesh, the shield mesh for reducing the effects of electronic cross-talk between nearby signal lines of the plurality of signal lines. Embodiments include the above and wherein the power and ground lines of the shield mesh are alternatively disposed and parallel to each other within a single metal layer of the substrate.
Other embodiments include an integrated circuit as described above generally and wherein the power and ground lines of the shield mesh are alternatively disposed in a first direction parallel to each other within a first metal layer of the substrate and wherein the power and ground lines of the shield mesh are also alternatively disposed in a second direction parallel to each other within a second metal layer of the substrate, the second metal layer being underneath the first metal layer and wherein the first and second directions are 90 degrees apart.